The invention relates to chemical mechanical polishing (CMP) of semiconductor wafer materials and, more particularly, to CMP compositions and methods for polishing metal interconnects on semiconductor wafers in the presence of dielectrics and barrier materials.
Typically, a semiconductor wafer is a wafer of silicon with a dielectric layer containing multiple trenches arranged to form a pattern for circuit interconnects within the dielectric layer. The pattern arrangements usually have a damascene structure or dual damascene structure. A barrier layer covers the patterned dielectric layer and a metal layer covers the barrier layer. The metal layer has at least sufficient thickness to fill the patterned trenches with metal to form circuit interconnects.
CMP processes often include multiple polishing steps. For example, a first step removes excess interconnect metals, such as copper at an initial high rate. After the first step removal, a second step polishing can remove metal that remains on the barrier layer outside of the metal interconnects. Subsequent polishing removes the barrier from an underlying dielectric layer of a semiconductor wafer to provide a planar polished surface on the dielectric layer and the metal interconnects.
The metal in a trench or trough on the semiconductor substrate provides a metal line forming a metal circuit. One of the problems to be overcome is that the polishing operation tends to remove metal from each trench or trough, causing recessed dishing of such metal. Dishing is undesirable as it causes variations in the critical dimensions of the metal circuit. To reduce dishing, polishing is performed at a lower polishing pressure. However, merely reducing the polishing pressure would require that polishing continue for a lengthened duration; and dishing would continue to be produced for the entire lengthened duration.
Schroeder et al., in US Pat. Pub. No. 2003/0228763, disclose a method of using amphiphilic nonionic surfactants for impacting copper dishing and dielectric erosion. As patterned wafer polishing technology moves to decreased line widths, there is a continuing need for a method to reduce dishing of metal in trenches or troughs without lengthening the duration of the polishing operation. Furthermore, there is a need for polishing compositions that leave a surface clear of interconnect metal residue after a short polishing time.